| Application | How DSS is leveraged | |-------------|----------------------| | | Most of the time the display shows a static clock face → 30 Hz, saving battery. When the user scrolls through notifications or starts a workout animation, the driver jumps to 60 Hz for fluid motion. | | Industrial HMI panels | Static schematics stay in low‑frequency mode; when a video feed or live graph appears, the panel instantly upgrades to high‑frequency to avoid motion artifacts. | | E‑book reader with color LCD | Page‑turn animations are rendered at 60 Hz, but the static text pages revert to 30 Hz, extending the device’s runtime. |
HX8872-F_DS_v1.0.pdf (approx. 2.1 MB)
Look for the ball/pin assignment diagram. For COG (Chip on Glass) versions, note that some pins are "No Connect" (NC) or require specific pull-up/down resistors. Pay special attention to: hx8872-f datasheet pdf
No third-party article can replace the authoritative data inside the official PDF. Use this guide to navigate the document efficiently, and your display project will achieve first-pass success.
If you need a custom scan‑rate (e.g., 50 Hz for a specific panel), set SCAN_SEL = 0b11 and adjust USER_DIV accordingly; the datasheet provides the exact PLL divisor‑to‑frequency mapping in Table 4‑5. | Application | How DSS is leveraged |
The datasheet clearly states: VCI must rise before or at the same time as VDDI. If VDDI rises alone, the internal ESD structures may latch up. Always follow Figure 28 (Power-on Sequence) in the .
// 2) Sensitivity: trigger when > 30 (out of 255) pixel‑diff per frame hx8872_write_reg(HX8872_REG_DSS_THR, 0x1E); | | E‑book reader with color LCD |
| Benefit | How it helps a design | |---------|----------------------| | – When the display shows a static image (menus, clock faces, etc.), the driver can drop to the low‑frequency mode, cutting the LCD’s back‑plane power consumption by up to 30 % . | | User‑experience boost – As soon as motion is detected (e.g., a video starts, a game begins, a UI scrolls), the driver instantly flips to the high‑frequency mode, eliminating perceived lag or ghosting. | | No extra hardware – The switch is performed internally by writing a single register (the DYN_SCAN_CTRL register) via the standard 8‑bit parallel/serial interface; no extra external clock generator or MCU intervention is required. | | Seamless transition – The datasheet guarantees ≤ 2 ms transition time, so the user never sees a flicker or glitch during the mode change. | | Fine‑grained control – The driver provides three selectable scan‑rate steps (e.g., 30 Hz, 45 Hz, 60 Hz) and a “user‑defined” slot where you can program any frequency within the 20‑80 Hz window by adjusting the internal PLL divisor. |
Clock and data lines for Mini-LVDS output to the source drivers. Power management pins (VCC, VSS).