Here is the complete code for a 3-bit multiplier using the structural approach. We generate partial products using AND gates and use instances of the full adder to sum them.
The multiplication of binary numbers follows the same "shift and add" principle as decimal multiplication. For two 3-bit numbers, the process involves: Partial Product Generation : Nine AND gates are used to multiply each bit of by each bit of Partial Product Reduction/Addition : These products are then summed using a network of Half Adders (HA) and Full Adders (FA)
endmodule
cap P sub 5 cap P sub 4 cap P sub 3 cap P sub 2 cap P sub 1 cap P sub 0 Multiplier Logic and Architecture
module full_adder ( input a, b, cin, output sum, cout ); assign sum = a ^ b ^ cin; assign cout = (a & b) | (b & cin) | (a & cin); endmodule 3-bit multiplier verilog code
Now, let's implement a sequential version that uses a clock and takes 3 clock cycles to compute.
vsim -do run.do
// Helper modules module half_adder ( input a, b, output sum, carry ); assign sum = a ^ b; assign carry = a & b; endmodule
In a 3-bit multiplier, the critical path (the longest route a signal travels) goes through the cascaded adders. As bit-width increases, designers often switch from this "Ripple Carry" style to Carry Look-ahead or Wallace Tree architectures to reduce latency. Here is the complete code for a 3-bit
Let’s look at a manual example: multiplying $A (A_2A_1A_0)$ by $B (B_2B_1B_0)$.
The 3-bit multiplier is a perfect pedagogical tool. It introduces: For two 3-bit numbers, the process involves: Partial