Synopsys Design Compiler Tutorial Site

dc_shell -topo # for topographical mode (more accurate) dc_shell # normal mode

compile_ultra

write_script -output mapped/design_cons.tcl synopsys design compiler tutorial

Always check your logs for inferred latches. Unless intentional, latches are a nightmare for timing. dc_shell -topo # for topographical mode (more accurate)

After running Design Compiler, you can analyze the synthesis results using the report files generated by the tool. The report files provide information on the design metrics, such as area, power, and performance. such as area